An important aim of ongoing research in the semiconductor industry is increasing semiconductor performance while decreasing power consumption in semiconductor devices. Planar transistors, such as metal oxide semiconductor field effect transistors (MOSFETs) are particularly well suited for use in high-density integrated circuits. As the size of MOSFETs and other devices decrease, the dimensions of source/drain regions, channel regions, and gate electrodes of the devices, also decrease.
The design of ever-smaller planar transistors with short channel lengths makes it necessary to provide very shallow source/drain junctions. Shallow junctions are necessary to avoid lateral diffusion of implanted dopants into the channel, since such diffusion disadvantageously contributes to leakage currents and poor breakdown performance. Shallow source/drain junctions, with a thickness of about 30 nm to 100 nm, are generally required for acceptable performance in short channel devices.
Silicon-on-insulator (SOI) technology allows the formation of high-speed, shallow-junction devices. In addition, SOI devices improve performance by reducing parasitic junction capacitance.
In a SOI substrate, a buried oxide (BOX) film made of silicon oxide is formed on single crystal silicon, and a single crystal silicon thin film is formed thereon. Various methods for fabricating such SOI substrates are known. One such method is Separation-by-Implanted Oxygen (SIMOX), wherein oxygen is ion implanted into a single crystal silicon substrate to form a BOX film.
Another method of forming a SOI substrate is wafer bonding, wherein two semiconductor substrates with silicon oxide surface layers are bonded together at the silicon oxide surfaces to form a BOX layer between the two semiconductor substrates.
Another SOI technique is Smart Cut®, which also involves bonding semiconductor substrates through oxide layers. In the Smart Cut® method, one of the semiconductor substrates is doped with hydrogen ions prior to bonding. The hydrogen ion doping subsequently allows the hydrogen ion doped substrate to be split from the bonded substrates leaving behind a thin layer of silicon on the surface.
Shallow junction transistors use shallow trench isolation (STI) techniques to separate devices and circuits. STI techniques significantly increase manufacturing cost because the STI process consists of a number of processing steps and apparatuses, such as thermal oxidation, silicon nitride chemical vapor deposition (CVD), silicon nitride wet etch, reactive ion etch (RIE), high density plasma (HDP) silicon oxide deposition, wet clean, chemical-mechanical polishing (CMP), and photolithography. The uniformity and yield of wafers is also a concern in view of the additional processing steps required for STI processing.
Mesa isolation processing is an alternative to STI to electrically isolate adjacent semiconductor devices formed on a common substrate. In mesa processing, the silicon layer between adjacent semiconductor devices are removed by etching. However, the exposed silicon layer sidewalls of the semiconductor device are susceptible to current leakage. Thus, mesa isolation processing comprises fewer manufacturing steps to isolate adjacent semiconductor devices than STI processing.
The term semiconductor devices, as used herein, is not to be limited to the specifically disclosed embodiments. Semiconductor devices, as used herein, include a wide variety of electronic devices including flip chips, flip chip/package assemblies, transistors, capacitors, microprocessors, random access memories, etc. In general, semiconductor devices refer to any electrical device comprising semiconductors.